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preliminary TTR622c/ ttr621c 2010/06/11 page 1--34 ver. 4.0 a/d mcu
preliminary TTR622c/ ttr621c 2010/06/11 page 2--34 ver. 4.0 .general description .......................................................................................................... 3 .general description .......................................................................................................... 3 .features ............................................................................................................................. 3 .application ....................................................................................................................... 3 .pin assi gnment................................................................................................................ ..... 4 .ac / dc char acteristics ....................................................................................................... 8 .absolutely max. ratings ....................................................................................................... .........8 .d.c. characteristics .......................................................................................................... ............8 .a.c. characteristics .......................................................................................................... ............9 .block diagram................................................................................................................. ... 10 .function desc ription .......................................................................................................... 11 1 map of memory and i/os....................................................................................................... ......11 2 i/o map table ................................................................................................................ .........13 3 system control register..............................................................................................15 4 system clock control register ...............................................................................15 5 low voltage reset ............................................................................................................ ...........17 6 i/o register................................................................................................................. ...........18 a. port a ...................................................................................................................... .............18 b. port b & port e............................................................................................................. .......20 c. port c/ port f .............................................................................................................. .........21 d. port d...................................................................................................................... .............21 7 a/d function description ..................................................................................................... ........21 8 8-bit and 16-bit timer/count er function description...................................................................21 9 pwm control circuit .......................................................................................................21 10 time base timer............................................................................................................. .............21 11 watch dog timer............................................................................................................. ............21 12 reset plan.................................................................................................................. ............21 .application diagram .......................................................................................................... 2 1 .mask opti on table ............................................................................................................. .. 21 .rc oscillator resistor vs. frequency table ........................................................................ 21 .order information ................................................................................................. 21 .revise history?????.???????? ??????????????.......21 4
preliminary TTR622c/ ttr621c 2010/06/11 page 3--34 ver. 4.0 general description the mcu provides cost effective for adc application it designs by lsi high technology with low power process features ? use 4-bit cpu core ? operating voltage - (ttu621 c /ttu622 c )mask type 2.2v-5.5v (fsys=4mhz) 3.3v-5.5v (fsys=8mhz) - (ttr621 c /TTR622 c )otp type 2.2v-5.5v (fsys=4mhz) 3.3v-5.5v (fsys=8mhz) ? oscillator type mask option C resonator oscillator 1m-8mhz(external capacitor) C built-in rc oscillator external resistor internal capacitor (400k-4mhz ) C external clock input(osch) C (ttu622 c /TTR622 c )external 32768hz cr ystal oscillator C internal rc oscillator 16khz ? (ttu621 c /ttr621 c )user rom 2k*16 ram 128*4 (ttu622 c /TTR622 c )user rom 4k*16 ram 256*4 ? built-in (ttu621 c /ttr621 c ) 2 stacks (ttu622 c /TTR622 c ) 4 stacks ? built-in a time base with internal interrupt ? built-in watch dog timer ? built-in programming frequency divi der function for buzzer function ? stop function and sleep function feature to reduce power consumption ? (ttu621 c /ttr621 c )built-in 1 set 8-bit timer/ counter with auto-reload ? (ttu622 c /TTR622 c )built-in 2 set 8-bit timer/counter with auto-reload (share with 16-bit timer/counter) ? (ttu621 c /ttr621 c )built-in 1 set 8-bit pwm ? (ttu622 c /TTR622 c )built-in 2 set 8-bit pwm ? low voltage reset function ? (ttu621 c /ttr621 c )built-in 8 bits adc 4 channels (with internal interrupt function conversion time is 72us @4mhz) (8 -bit resolution and 7-bit accuracy) ? (ttu622 c /TTR622 c )built-in 8 bits adc 8 channels (with internal interrupt function conversion time is 64us @4mhz) (8 -bit resolution and 7-bit accuracy) ? (ttu621 c /ttr621 c )13 i/o ports (ttu622 c /TTR622 c )23 i/o ports ? provide external reset pi n and internal reset pin ? provide (ttu621 c /ttr621 c )18-pin dip/sop (ttu622 c /TTR622 c ) 24/28-pin sdip/sop application z electric appliances controller z consumer products z toy controller
preliminary TTR622c/ ttr621c 2010/06/11 page 4--34 ver. 4.0 .pin assignment (ttu621 c /ttr621 c ) (ttu622 c /TTR622 c ) 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 pc0/bz pc1/bzb pa3 pa2 pb3/an3 pb2/an2 pb1/an1 pb0/an0 vss p a1/tmck pa0/int0 pd0 pc3/pwm2 pd1 pd2 osco osci vdd 20-dip/sop pc2/pwm1 10 resetb 11 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 pc0/bz pc1/bzb pa3 pa2 pb3/an3 pb2/an2 pb1/an1 pb0/an0 vss p a1/tmck pa0/int0 pd0 pc3/pwm2 osco osci vdd resetb pc2/pwm1 18-dip/sop ttu621c/ r621c ttu621-f1 ttu622c/ r622c
preliminary TTR622c/ ttr621c 2010/06/11 page 5--34 ver. 4.0
preliminary TTR622c/ ttr621c 2010/06/11 page 6--34 ver. 4.0 . pin description (ttu621 c /ttr621 c ) name i/o description pins pa0/int0 i/o general purpose i/o port hysteresis input pull high 100kohm @3v selected by software there can be selected as exte rnal interrupt input function 1 pa1/ tmck i/o general purpose i/o port hysteresis input pull high 100kohm @3v selected by software there can be selected as external wake -up function or external clock input for timer/counter1 circuit 1 pa2-pa3 i/o general purpose i/o port hysteresis input pull high 100kohm @3v selected by software there can be selected as external wake-up function 2 pd0 i/o general purpose i/o port hysteresis input pull high 100kohm @3v selected by software there can be selected as external wake-up function 1 rstb i external reset pin low active 1 vss p digital ground pin 1 vss p analog ground pin 1 pb0/an0 pb1/an1 pb2/an2 pb3/an3 i/o general purpose i/o port hysteresis input pull high 100kohm @3v selected by software with wake up function selected by software programming(falling edge trigger) there can be selected as an a/d input the i/o function and pull-high resistor are disabled automatically 4 pc0/bz pc1/bzb i/o general purpose i/o port hysteresis input pull high 100kohm @3v selected by software with wake up function selected by software programming(falling edge trigger) ther can be selected as buzzer func tion select by software programming 2 pc2/pwma1 pc3/pwma2 i/o general purpose i/o port hysteresis input pull high 100kohm @3v selected by software with wake up function selected by software programming (falling edge trigger) ther can be selected as pwm func tion select by software programming 2 vdd p analog power pin 1 vdd p digital power pin 1 osci i crystal type: crystal input rc type: rc oscillator input external clock input 1 osco o crystal type: crystal output rc type: oscillator frequency divided by 2 is available on osco to synchronize other logic or used for testing purpose. 1 total pin 20 note ? please notice input pin pull low/high or out put pin driving current capacity in this table
preliminary TTR622c/ ttr621c 2010/06/11 page 7--34 ver. 4.0 (ttu622 c /TTR622 c ) name i/o description pins pa0/int0 i/o general purpose i/o port hysteresis input pull high 100kohm @5v selected by software there can be selected as exte rnal interrupt input function 1 pa1/ tmck i/o general purpose i/o port hysteresis input pull high 100kohm @5v selected by software it can be selected as external wake-u p function or external clock input for timer/counter1 circuit 1 pa2/rtci pa3/rtco i/o general purpose i/o port hysteresis input pull high 100kohm @5v selected by software there can be selected as external wake-up function ther can be selected as 32768hz crystal oscillator function programed by mask option 2 rstb/ vpp i external reset pin hysteresis input without pull high low active 1 vss p digital ground pin 1 vss p analog ground pin 1 pb0/an0 pb1/an1 pb2/an2 pb3/an3 i/o general purpose i/o port hysteresis input pull high 100kohm @5v selected by software with wake up function selected by software programming(falling edge trigger) there can be selected as an a/d input the i/o function and pull-high resistor are disabled automatically 4 pe0/an4 pe1/an5 pe2/an6 pe3/an7 i/o general purpose i/o port hysteresis input pull high 100kohm @5v selected by software with wake up function selected by software programming(falling edge trigger) there can be selected as an a/d input the i/o function and pull-high resistor are disabled automatically 4 vdd p analog power pin 1 vdd p digital power pin 1 pc0/bz pc1/bzb i/o general purpose i/o port hysteresis input pull high 100kohm @5v selected by software with wake up function selected by software programming(falling edge trigger) ther can be selected as buzzer func tion select by software programming 2 pc2/pwma1 pc3/pwma2 i/o general purpose i/o port hysteresis input pull high 100kohm @5v selected by software with wake up function selected by software programming (falling edge trigger) ther can be selected as pwm func tion select by software programming 2 pf0/pwmb1 pf1/pwmb2 i/o general purpose i/o port hysteresis input pull high 100kohm @5v selected by software with wake up function selected by software programming (falling edge trigger) ther can be selected as pwm func tion select by software programming 2 pf2 i/o general purpose i/o port hysteresis input pull high 100kohm @5v selected by software there can be selected as external wake-up function 1 osci i crystal type: crystal input rc type: rc oscillator input external clock input 1 osco o crystal type: crystal output rc type: oscillator frequency divided by 2 is available on osco to synchronize other logic or used for testing purpose. 1 pd0-pd3 i/o general purpose i/o port hysteresis input pull high 100kohm @5v selected by software there can be selected as external wake-up function 4 total pin 30 note ? please notice input pin pull low/high or out put pin driving current capacity in this table
preliminary TTR622c/ ttr621c 2010/06/11 page 8--34 ver. 4.0 . ac / dc characteristics .absolutely max. ratings item symbol rating unit operating temperature top -20 - + 95 storage temperature tsto -50 - +125 supply voltage vdd 6.0 v voltage to input terminal vin vss-0.3 to vdd+0.3 v .d.c. characteristics condition : ta= 25 3 rh Q 65 % vdd = 3v vss=0v item symb ol condition min typ max unit operating voltage vdd1 (ttu621 c /ttu622 c )fsys=4mhz 2.2 3.0 5.5 v operating voltage vdd1 (ttr621 c /TTR622 c )fsys=4mhz 2.0 3.0 5.5 v operating voltage vdd2 fsys=8mhz 3.0 5.0 5.5 v power consumption current i opr1 system clock at 8mhz resonator no load @5.0v adc off 4.0 8.0 ma power consumption current i opr2 system clock at 4mhz resonator no load @5.0v adc off 2.5 5.0 ma power consumption current i opr3 system clock at 4mhz rc oscillator no load @5.0v adc off 2.5 5.0 ma power consumption current i opr4 system clock at 32khz crystal oscillator no load @3.0v adc off 20 40 ua adc power consumption i ad1 additional power consumption when adc use(adc clock is 1mhz and vdd=3v) 0.5 1 ma adc power consumption i ad2 additional power consumption when adc use(adc clock is 1mhz and vdd=5v) 1.5 3 ma halt current ist2 system halt no load @3.0v wdt disable 1 ua input low voltage for input and i/o port v il1 0 0.3vdd v input high voltage for input and i/o port v ih1 0.7vdd vdd v input low voltage for resb pin v il2 0 0.4vdd v input high voltage for resb pin v ih2 0.9vdd vdd v i/o port sink current i ol1 v ol =0.1vdd @5.0v 4 8 16 ma i/o port source current i oh1 v oh =0.9vdd @5.0v 2 4 8 ma pull high resistance r up @5v 100 150 200 kohm resonator oscillator sustain voltage v su 2.3 v
preliminary TTR622c/ ttr621c 2010/06/11 page 9--34 ver. 4.0 lvr current i lvr @ 3.0v 70 100 ua a/d input voltage v adi (vref=vdd) 0 vdd v a/d conversion error e adc when vdd from 2.7v-5.5v 0.5 1 lsb .a.c. characteristics item symbol condition min typ max unit system clock1 f sys1 resonator oscillator @3.0v 4 mhz system clock2 f sys2 rc oscillator @3.0v external resistor 4 mhz watch dog clock f wdt (internal oscillator circuit) 8 16 32 khz external reset low pulse width t res 1 us adc conversion time t adc at 4mhz system clock adc clock is 1mhz 64 us
preliminary TTR622c/ ttr621c 2010/06/11 page 10--34 ver. 4.0 . block diagram rc osc./ resonator 4-bit cpu core su621c-1 working ram i/o port eprom / rom timer/ time base adc low voltage reset internal power on reset watch dog timer pwm pfd external reset cicuit external interrupt input
preliminary TTR622c/ ttr621c 2010/06/11 page 11--34 ver. 4.0 . function description 1 map of memory and i/os (ttu621 c /ttr621 c ) su621c-g1 ram reserved data memory map 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00ah 00bh 00ch 00dh 00eh 00fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01ah 01bh 01ch 01dh 01eh 01fh 020h 09fh 0a0h 11fh 120h 121h 12ah fffh (dp1) a tb1 tb2 tb3 dpl dpm dph ps intf intc pa0&ctl pac pa pbc pb pcc pc pdc pd tbc/bzc tmr1l tmr1h tmr1c pwm1dl pwm1dh adl adh adctl0 adctl1 pwmc ad-sel0 7ff 002 progrom memory map 800 fff reserved 001 000 reset vector intb vector on-chip program memory reserved reserved pwmck
preliminary TTR622c/ ttr621c 2010/06/11 page 12--34 ver. 4.0 (ttu622 c /TTR622 c ) su622c-g1 ram reserved 002 progrom memory map fff 001 000 reset vector intb vector on-chip program memory data memory map 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00ah 00bh 00ch 00dh 00eh 00fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01ah 01bh 01ch 01dh 01eh 01fh 020h 11fh 120h 121h 122h 123h 124h 125h 126h 127h 128h 129h 12ah fffh (dp1) a tb1 tb2 tb3 dpl dpm dph ps intf intc pa0&ctl pac pa pbc pb pcc pc pdc pd pec pe tbc/bzc tmr1l tmr1h tmr1c pwm1dl pwm1dh adl adh adctl0 adctl1 pwmc ad-sel0 ad-sel1 pfc pf pwm2dl pwm2dh tmr2l tmr2h tmr2c pwmck
preliminary TTR622c/ ttr621c 2010/06/11 page 13--34 ver. 4.0 2i/o map table address resister bit3 bit2 bit1 bit0 initial state 008h ps x h/l sleep stop u100 x r/w r/w r/w 009h intf pa0f tmr1f tmr2f tbf 0000 r/w r/w r/w r/w 00ah intc pa0ie tmr1ie tmr2ie tbie 0000 r/w r/w r/w r/w 00bh pa0&ctl rf1 rf0 lvren lvrc 0010 r/w r/w r/w r/w 00ch pac pac3 pac2 pac1 pac0 1111 r/w r/w r/w r/w 00dh pa pa3 pa2 pa1 pa0 1111 r/w r/w r/w r/w 00eh pbc pbc3 pbc2 pbc1 pbc0 1111 r/w r/w r/w r/w 00fh pb pb3 pb2 pb1 pb0 1111 r/w r/w r/w r/w 010h pcc pcc3 pcc2 pcc1 pcc0 1111 r/w r/w r/w r/w 011h pc pc3 pc2 pc1 pc0 1111 r/w r/w r/w r/w 012h pdc pdc3 pdc2 pdc1 pdc0 1111 r/w r/w r/w r/w 013h pd pd3 pd2 pd1 pd0 1111 r/w r/w r/w r/w 014h pec pec3 pec2 pec1 pec0 1111 r/w r/w r/w r/w 015h pe pe3 pe2 pe1 pe0 1111 r/w r/w r/w r/w 016h tbc/bzc bzen tb2 tb1 tb0 0000 r/w r/w r/w r/w 017h tmr1l tmr1_3 tmr1_2 tmr1_1 tmr1_0 0000 r/w r/w r/w r/w 018h tmr1h tmr1_7 tmr1_6 tmr1_5 tmr1_4 0000 r/w r/w r/w r/w 019h tmr1c tm1ld t1ck1 t1ck0 tm1en 0000 r/w r/w r/w r/w 01ah pwmadl dty13 dty12 dty11 dty10 0000 r/w r/w r/w r/w 01bh pwmadh dty17 dty16 dty15 dty14 0000 r/w r/w r/w r/w 01ch adl ad3 ad2 ad1 ad0 0000
preliminary TTR622c/ ttr621c 2010/06/11 page 14--34 ver. 4.0 r r r r 01dh adh ad7 ad6 ad5 ad4 0000 r r r r 01eh adctl0 aden ch2 ch1 ch0 0000 r/w r/w r/w r/w 01fh adctl1 adie adf adck1 adck0 0000 r/w r/w r/w r/w 120h pwmc pwma2en pwma1en pwma2dc pwma1dc 0000 r/w r/w r/w r/w 121h ad-sel0 an3/pb3 an2/pb2 an1/pb1 an0/pb0 0000 r/w r/w r/w r/w 122h ad-sel1 an7/pe3 an6/pe2 an5/pe1 an4/pe0 0000 r/w r/w r/w r/w 123h pfc x pfc2 pfc1 pfc0 u111 x r/w r/w r/w 124h pf x pf2 pf1 pf0 u111 x r/w r/w r/w 125h pwmbdl dty23 dty22 dty21 dty20 0000 r/w r/w r/w r/w 126h pwmbdh dty27 dty26 dty25 dty24 0000 r/w r/w r/w r/w 127h tmr2l tmr2_3 tmr2_2 tmr2_1 tmr2_0 0000 r/w r/w r/w r/w 128h tmr2h tmr2_7 tmr2_6 tmr2_5 tmr2_4 0000 r/w r/w r/w r/w 129h tmr2c tm2ld t2ck1 t2ck0 tm2en 0000 r/w r/w r/w r/w 12ah pwmck ck2_s1 ck2_s0 ck1_s1 ck1_s0 0000 r/w r/w r/w r/w
preliminary TTR622c/ ttr621c 2010/06/11 page 15--34 ver. 4.0 3 system control register address resister bit3 bit2 bit1 bit0 initial state 008h ps x h/l sleep stop 1100 x r/w r/w r/w stop high active (all oscillator circuit is not active ) sleep high active operating mode function status sleep(high active) stop(high active) oscillator operating stopped cpu internal status retain the status memory flag register i/o retain the status program counter hold the executed address timer/counter/ time base timer operated stopped & retain watch-dog enable retain the status release condition( and clear stop or sleep flag) pa0-int/ pa&pb pc&pd &pe&pf port wake-up / adc-int/ tmr1-int/ tmr2-int/ tb-int pa0-int/ pa&pb &pc&pd &pe&pf port wake-up 4 system clock control register address resister bit3 bit2 bit1 bit0 initial state 008h ps x h/l sleep stop u100 x r/w r/w r/w h/l oscillator speed control register flag function h/l low oscillator low speed mode (oscl) high oscillator high speed mode (osch) (ttu621 c /ttr621 c ) ext. resonator h/l fsys oscl osch control su621c-j mux int. rc 16k oscl ext. rc osc. ext. clock input osch mask option
preliminary TTR622c/ ttr621c 2010/06/11 page 16--34 ver. 4.0 (ttu622 c /TTR622 c ) * x rtc(ext. 32k crystal) r int. 16krc osc. ? off * oscl is always on except stop=high * M sleep mode r h/l ? low speed mode ?r osch ? off * external rc oscillator mode r osco pin ? rc osc. l?? clock ? * rtc oscillation stable time needs 0.5sec ~2 sec th at depends on operating voltage and ic process. ext. resonator h/l fsys oscl osch control su622c-j mux oscl ext. rc osc. ext. clock input osch mask option mux ext. 32k crystal int. 16k rc osc. /2 mask option
preliminary TTR622c/ ttr621c 2010/06/11 page 17--34 ver. 4.0 low voltage reset address resister bit3 bit2 bit1 bit0 initial state 00bh pa0&ctl rf1 rf0 lvren lvrc 0010 r/w r/w r/w r/w flag function lvren low disable lvr function high enable lvr function lvrc low select v+ level for lvr when lvren=1 ttu622 : lvr ??y? vdd < 2.4v 10% TTR622 : lvr ??y? vdd < 2.2v 10% high select v+ level for lvr when lvren=1 lvr ??y? vdd < 3.0v 10% (ttu622 c ) lvr ??y? - vdd < 2.4v 10% - vdd < 3.0v 10% (TTR622 c ) lvr ??y? - vdd < 2.2v 10% - vdd < 3.0v 10% su621c-3 band gap trim + _ lvren r3 r2 reset vref v+ vdd lvrc debounce 62.5-125us r1 use internal rc16k
preliminary TTR622c/ ttr621c 2010/06/11 page 18--34 ver. 4.0 5 i/o register a. port a address resister bit3 bit2 bit1 bit0 initial state 009h intf pa0f tmr1f tmr2f tbf 0000 r/w r/w r/w r/w 00ah intc pa0ie tmr1ie tmr2ie tbie 0000 r/w r/w r/w r/w 00bh pa0&ctl rf1 rf0 lvren lvrc 0010 r/w r/w r/w r/w 00ch pac pac3 pac2 pac1 pac0 1111 r/w r/w r/w r/w 00dh pa pa3 pa2 pa1 pa0 1111 r/w r/w r/w r/w pac ? i/o mode high r input mode pa0 input mode r interrupt (rising and falling edge trigger) ?yM stop or sleep mode r? pin wake up pa0f flag write bit ?0? r clear ?0? ? write bit ?1? r set ?1? rf0/rf1 interrupt trigger ? pa1 i/o port data input mode r dreg ?? pull high function pin pull high function r wake up function ?D pin ? timer/counter clock input rf1 rf0 trigger 0 0 falling edge 0 1 rising edge 1 0 falling & rising edge 1 1 falling & rising edge 100k@5v data reg. (dreg) su621c-61 4 input control address i/o control reg. (ioreg) address 1. ioreg=0, output mode 2. ioreg=1, input mode - dreg=0, without pull high - dreg=1, with pull high pull high control int rising and falling edge detecter pa0ie pa0f 009hw '0' clr pad 1. cpu read (dreg) data when ioreg=0 (at output mode) 2. cpu read the pad data when ioreg=1 (at input mode) rf1 | rf0
preliminary TTR622c/ ttr621c 2010/06/11 page 19--34 ver. 4.0 pa2/pa3 i/o port data input mode r dreg ?? pull high function pin pull high function r wake up function ?D?? mask option x 32768hz crystal oscillator pin 100k@ 5v data reg. (dreg) su621c-94 4 input control address i/o control reg. (ioreg) address 1. ioreg=0, output mode 2. ioreg=1, input mode - dreg=0, without pull high - dreg=1, with pull high pull high control wake up 1. cpu read (dreg) data when ioreg=0 (at output mode) 2. cpu read the pad data when ioreg=1 (at input mode) osc. circuit option(rtc) * rtc=1 - with rtc function - no pull high function - ioreg=1 * rtc=0 - normal i/o function pad 100k@ 5v data reg. (dreg) su621c-95 4 input control address i/o control reg. (ioreg) address 1. ioreg=0, output mode 2. ioreg=1, input mode - dreg=0, without pull high - dreg=1, with pull high pull high control wake up 1. cpu read (dreg) data when ioreg=0 (at output mode) 2. cpu read the pad data when ioreg=1 (at input mode) to timer/counter1 pad
preliminary TTR622c/ ttr621c 2010/06/11 page 20--34 ver. 4.0 b. port b & port e address resister bit3 bit2 bit1 bit0 initial state 00eh pbc pbc3 pbc2 pbc1 pbc0 1111 r/w r/w r/w r/w 00fh pb pb3 pb2 pb1 pb0 1111 r/w r/w r/w r/w 014h pec pec3 pec2 pec1 pec0 1111 r/w r/w r/w r/w 015h pe pe3 pe2 pe1 pe0 1111 r/w r/w r/w r/w 01eh adctl0 aden ch2 ch1 ch0 0000 r/w r/w r/w r/w 01fh adctl1 adie adf adck1 adck0 0000 r/w r/w r/w r/w 121h ad-sel0 an3/pb3 an2/pb2 an1/pb1 an0/pb0 0000 r/w r/w r/w r/w 122h ad-sel1 an7/pe3 an6/pe2 an5/pe1 an4/pe0 0000 r/w r/w r/w r/w pbc/ pec ? i/o mode high r input mode pb/ pe i/o port data input mode r (ad-selx=0) dreg ?? pull high function pin pull high function r wake up function ?D 100k@ 5v data reg. (dreg) su621c-92 4 input control address i/o control reg. (ioreg) address 1. ioreg=0, output mode 2. ioreg=1, input mode - dreg=0, without pull high - dreg=1, with pull high pull high control wake up 1. cpu read (dreg) data when ioreg=0 (at output mode) 2. cpu read the pad data when ioreg=1 (at input mode) to adc cell pad analog switch i/o pad cell analog switch of adc channel select ad convertor ad-selx ch2 ch1 ch0 0 1 analog switch i/o pad cell ad-selx 0 1 su621c-i
preliminary TTR622c/ ttr621c 2010/06/11 page 21--34 ver. 4.0 0 0 0 an0 0 0 1 an1 0 1 0 an2 0 1 1 an3 1 0 0 an4 1 0 1 an5 1 1 0 an6 1 1 1 an7 c. port c/ port f address resister bit3 bit2 bit1 bit0 initial state 010h pcc pcc3 pcc2 pcc1 pcc0 1111 r/w r/w r/w r/w 011h pc pc3 pc2 pc1 pc0 1111 r/w r/w r/w r/w 016h tbc/bzc bzen tb2 tb1 tb0 0000 r/w r/w r/w r/w 120h pwmc pwmben pwmaen pwmbdc pwmadc 0000 r/w r/w r/w r/w 123h pf x pf2 pf1 pf0 u111 x r/w r/w r/w 124h pfc x pfc2 pfc1 pfc0 u111 x r/w r/w r/w pcc/ pfc ? i/o mode high r input mode pc i/o port data input mode r dreg ?? pull high function pin pull high function r wake up function output mode & bzen=1 r dreg ? buzzer/ pfd ? dreg=1 r?l? dreg=0 r? low ?D output mode & pwmxen=1 r , (ioreg=0) pwm ? , (ioreg=1) t input mode ch2 ch1 ch0 adc channel selection su621c-96 100k@5v data reg. (dreg) 4 input control address i/o control reg. (ioreg) address 1. ioreg=0, output port mode 2. ioreg=0, bzen=1 - dreg=1, bz output enable - dreg=0, bz output disable 3. ioreg=1, input mode - dreg=0, without pull high - dreg=1, with pull high pull high control data reg. (dreg) input control pull high control 1. cpu read (dreg) data when ioreg=0 (at output mode) 2. cpu read the pad data when ioreg=1 (at input mode) bzen bz/ pfd frequency wake up
preliminary TTR622c/ ttr621c 2010/06/11 page 22--34 ver. 4.0 flag function bzen low pc0/pc1 without buzzer function high pc0/pc1 with buzzer function and enable buzzer frequency output through pc0 pad pwmaen low pc2/ pc3 without pwm function i/o function only high pc2/ pc3 with pwm function or input function are controlled as below: - if (ioreg)=0 then enable pwma frequency output through pad - if (ioreg)=1 then at input function mode pwmben low pf0/ pf1 without pwm function i/o function only high pf0/ pf1 with pwm function or input function are controlled as below: - if (ioreg)=0 then enable pwmb frequency output through pad - if (ioreg)=1 then at input function mode d. port d address resister bit3 bit2 bit1 bit0 initial state 012h pdc pdc3 pdc2 pdc1 pdc0 1111 r/w r/w r/w r/w 013h pd pd3 pd2 pd1 pd0 1111 r/w r/w r/w r/w pdc ? i/o mode high r input mode pd i/o port data input mode r dreg ?? pull high function pin pull high function r wake up function ?D su621c-96 100k@5v data reg. (dreg) 4 input control address i/o control reg. (ioreg) address 1. ioreg=0, output port mode 2. ioreg=0, pwmxen=1 pwm output 3. ioreg=1, input mode - dreg=0, without pull high - dreg=1, with pull high pull high control data reg. (dreg) input control pull high control 1. cpu read (dreg) data when ioreg=0 (at output mode) 2. cpu read the pad data when ioreg=1 (at input mode) pwmaen/pwmbe pwma/pwmb frequency wake up 100k@5v data reg. (dreg) su621c-91 4 input control address i/o control reg. (ioreg) address 1. ioreg=0, output mode 2. ioreg=1, input mode - dreg=0, without pull high - dreg=1, with pull high pull high control wake up 1. cpu read (dreg) data when ioreg=0 (at output mode) 2. cpu read the pad data when ioreg=1 (at input mode) pad
preliminary TTR622c/ ttr621c 2010/06/11 page 23--34 ver. 4.0 6 a/d function description address resister bit3 bit2 bit1 bit0 initial state 01ch adl ad3 ad2 ad1 ad0 0000 r r r r 01dh adh ad7 ad6 ad5 ad4 0000 r r r r 01eh adctl0 aden ch2 ch1 ch0 0000 r/w r/w r/w r/w 01fh adctl1 adie adf adck1 adck0 0000 r/w r/w r/w r/w adl/adh (ad0-ad7) a/d data 01ch port write ?r?? adc start conversion 01dh port write ?r?? cpu sleep adc start conversion adctl0/ adctl1 a/d control register flag function adie low disable internal interrupt high enable internal interrupt adf low normal mode high a/d conversion complete flag flag write bit ?0? r clear ?0? ? write bit ?1? r set ?1? aden low disable a/d high enable a/d ch2 ch1 ch0 ch2/ch1/ch0 000 select an0 input 001 select an1 input 010 select an2 input 011 select an3 input 100 select an4 input 101 select an5 input 110 select an6 input 111 select an7 input adck1 adck0 adck1/ adck0 00 select oscl clock 01 select osch clock/4 10 select osch clock/16 11 select osch clock/64. adc conversion ? latch ?adl? ?adh? data oscl clock osch clock/4 osch clock/16 osch clock/64 su621c-b1 4 address adc data register adie adf interrupt clock set 01fhw '0' clear start aden mux. adck0 adck1 01chw 01chr 01dhr latch
preliminary TTR622c/ ttr621c 2010/06/11 page 24--34 ver. 4.0 7 8-bit and 16-bit timer/counter function description address resister bit3 bit2 bit1 bit0 initial state 009h intf pa0f tmr1f tmr2f tbf 0000 r/w r/w r/w r/w 00ah intc pa0ie tmr1ie tmr2ie tbie 0000 r/w r/w r/w r/w 017h tmr1l tmr1_3 tmr1_2 tmr1_1 tmr1_0 0000 r/w r/w r/w r/w 018h tmr1h tmr1_7 tmr1_6 tmr1_5 tmr1_4 0000 r/w r/w r/w r/w 019h tmr1c tm1ld t1ck1 t1ck0 tm1en 0000 r/w r/w r/w r/w 127h tmr2l tmr2_3 tmr2_2 tmr2_1 tmr2_0 0000 r/w r/w r/w r/w 128h tmr2h tmr2_7 tmr2_6 tmr2_5 tmr2_4 0000 r/w r/w r/w r/w 129h tmr2c tm2ld t2ck1 t2ck0 tm2en 0000 r/w r/w r/w r/w intf tmr1f/ tmr2f timer/counter overflow flag flag write bit ?0? r clear ?0? ? write bit ?1? r set ?1? intc tmr1ie/tmr2ie ? tmr1f/tmr2f ?? a interrupt tmr1l/ tmr1h/ tmr2l/ tmr2h timer/counter data timer/counter data r/w overflow r set interrupt flag tmr1f/tmr2f flag function tm1en low stop timer/counter1 high start timer/counter1 tm2en low stop timer/counter2 high start timer/counter2 tm1ld low without auto-reload function(timer/counter1) high with auto-reload function(timer/counter1) tm2ld low without auto-reload function(timer/counter2) high with auto-reload function(timer/counter2) t1ck1/ t1ck0 (t1ck1/ t1ck0) 00 select osch clock 01 select time base timer clock(oscl) 10 select pa1 exte rnal input clock 11 select time base timer overflow(tbov) t2ck1/ t2ck0 (t2ck1/ t2ck0) 00 select osch clock/4 01 select time base timer clock(oscl) 10 select pc3 exte rnal input clock 11 select time base timer overflow(tmr1ov)
preliminary TTR622c/ ttr621c 2010/06/11 page 25--34 ver. 4.0 (ttu621 c /ttr621 c ) (ttu622 c /TTR622 c ) tmr1en tmr1ie tmr 1f su621c-c1 interrupt mux. timer/counter1 4 t1ck0 control /2 pfd out t1ck1 oscl tbov pa1 osch tmr1en tmr1ie tmr 1f su621c-c2 interrupt mux. timer/counter1 4 t1ck0 control tmr2en tm2ie tm2f interrupt 4 timer/counter2 /2 pfd out t1ck1 mux. t2ck0 t2ck1 control /4 tmr1ov oscl tbov pa1 osch oscl pc3
preliminary TTR622c/ ttr621c 2010/06/11 page 26--34 ver. 4.0 8 pwm control circuit address resister bit3 bit2 bit1 bit0 initial state 01ah pwmadl dty13 dty12 dty11 dty10 0000 r/w r/w r/w r/w 01bh pwmadh dty17 dty16 dty15 dty14 0000 r/w r/w r/w r/w 120h pwmc pwmben pwmaen pwmbdc pwmadc 0000 r/w r/w r/w r/w 125h pwmbdl dty23 dty22 dty21 dty20 0000 r/w r/w r/w r/w 126h pwmbdh dty27 dty26 dty25 dty24 0000 r/w r/w r/w r/w 12ah pwmck ck2_s1 ck2_s0 ck1_s1 ck1_s0 0000 r/w r/w r/w r/w pwmadl pwmadh pwmbdl pwmbdh pwm duty register option 2 modes flag function pwmaen low disable pwma output high enable pwma output pwmben low disable pwmb output high enable pwmb output pwm a dc low pwm circuit in 4 duty mode when pwmaen is high state high pwm circuit in 2 duty mode when pwmaen is high state pwmbdc low pwm circuit in 4 duty mode when pwmben is high state high pwm circuit in 2 duty mode when pwmben is high state ck1_s1/ ck1_s0 select pwma input clock ck1_s1/ck1_s0 00 : external high frequency 01: external high frequency/4 10 : external high frequency/16 11: external high frequency/64 ck2_s1/ ck2_s0 select pwmb input clock ck2_s1/ck2_s0 00 : external high frequency 01: external high frequency/4 10 : external high frequency/16 11: external high frequency/64 4 duty cycle mode dty*7 dty*6 dty*5 dty*4 dty*3 dty*2 dty*1 dty*0 4 duty cycles 0 0 0 0 0 0 0 0 0/64+0/64+0/64+0/64 0 0 0 0 0 0 0 1 1/64+0/64+0/64+0/64 0 0 0 0 0 0 1 0 1/64+1/64+0/64+0/64 0 0 0 0 0 0 1 1 1/64+1/64+1/64+0/64 0 0 0 0 0 1 0 0 1/64+1/64+1/64+1/64 ? ? ? ? ? ? ? ? ? 0 1 0 0 0 0 0 1 17/64+16/64+16/64+16/64 0 1 0 0 0 0 1 0 17/64+17/64+16/64+16/64 0 1 0 0 0 0 1 1 17/64+17/64+17/64+16/64 0 1 0 0 0 1 0 0 17/64+17/64+17/64+17/64 ? ? ? ? ? ? ? ? ?
preliminary TTR622c/ ttr621c 2010/06/11 page 27--34 ver. 4.0 1 0 0 0 0 0 0 1 33/64+32/64+32/64+32/64 1 0 0 0 0 0 1 0 33/64+33/64+32/64+32/64 1 0 0 0 0 0 1 1 33/64+33/64+33/64+32/64 1 0 0 0 0 1 0 0 33/64+33/64+33/64+33/64 ? ? ? ? ? ? ? ? ? 1 1 0 0 0 0 0 1 49/64+48/64+48/64+48/64 1 1 0 0 0 0 1 0 49/64+49/64+48/64+48/64 1 1 0 0 0 0 1 1 49/64+49/64+49/64+48/64 1 1 0 0 0 1 0 0 49/64+49/64+49/64+49/64 ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 0 63/64+63/64+63/64+63/64 1 1 1 1 1 1 0 1 64/64+63/64+63/64+63/64 1 1 1 1 1 1 1 0 64/64+64/64+63/64+63/64 1 1 1 1 1 1 1 1 64/64+64/64+64/64+63/64 2 duty cycle mode dty*7 dty*6 dty*5 dty*4 dty*3 dty*2 dty*1 dty*0 2 duty cycles 0 0 0 0 0 0 0 0 0/128+0/128 0 0 0 0 0 0 0 1 1/128+0/128 0 0 0 0 0 0 1 0 1/128+1/128 0 0 0 0 0 0 1 1 2/128+1/128 0 0 0 0 0 1 0 0 2/128+2/128 ? ? ? ? ? ? ? ? ? 0 1 0 0 0 0 0 1 33/128+32/128 0 1 0 0 0 0 1 0 33/128+33/128 0 1 0 0 0 0 1 1 34/128+33/128 0 1 0 0 0 1 0 0 34/128+34/128 ? ? ? ? ? ? ? ? ? 1 0 0 0 0 0 0 1 65/128+64/128 1 0 0 0 0 0 1 0 65/128+65/128 1 0 0 0 0 0 1 1 66/128+65/128 1 0 0 0 0 1 0 0 66/128+66/128 ? ? ? ? ? ? ? ? ? 1 1 0 0 0 0 0 1 97/128+96/128 1 1 0 0 0 0 1 0 97/128+97/128 1 1 0 0 0 0 1 1 98/128+97/128 1 1 0 0 0 1 0 0 98/128+98/128 ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 0 126/128+126/128 1 1 1 1 1 1 0 1 127/128+126/128 1 1 1 1 1 1 1 0 127/128+127/128 1 1 1 1 1 1 1 1 128/128+127/128
preliminary TTR622c/ ttr621c 2010/06/11 page 28--34 ver. 4.0 9 time base timer address resister bit3 bit2 bit1 bit0 initial state 009h intf pa0f tmr1f tmr2f tbf 0000 r/w r/w r/w r/w 00ah intc pa0ie tmr1ie tmr2ie tbie 0000 r/w r/w r/w r/w 016h tbc/bzc bzen tb2 tb1 tb0 0000 r/w r/w r/w r/w tbf time base timer overflow flag flag write bit ?0? r clear ?0? ? write bit ?1? r set ?1? tbie time base timer interrupt enable control register tb0/ tb1/ tb2 time base timer input clock source select register 0 0 0 128hz 0 0 1 64hz 0 1 0 32hz 0 1 1 16hz 1 0 0 8hz 1 0 1 4hz 1 1 0 2hz 1 1 1 1hz ?? rtc mode ? time base timer ? power on ? stop mode wake-up ???? ?read 008h 008hr ? ?tl??_ * rtc oscillation stable time needs 0.5 sec ~2 sec th at depends on operating voltage and ic process. 10 watch dog timer address resister bit3 bit2 bit1 bit0 initial state 008h ps x h/l sleep stop u100 x r/w r/w r/w ? 008hw clear wdt D tb2 tb1 tb0 o/p tbie su621c-d1 interrupt oscl tbf /16384 mux tb0 | tb1 | tb2 wdten reset /8 clear 008hw tbov
preliminary TTR622c/ ttr621c 2010/06/11 page 29--34 ver. 4.0 reset plan reset ? 3 N a. internal reset b. external reset active low c. lvr reset ? reset high voltage to low voltage . application diagram . mask option table function option u621 c r621 c u622 c r622 c oscillator type resonator rc oscillator mask mask mask mask time base clock selection external 32k crystal oscillator internal rc oscillator x x mask mask lvr control lvr disable lvr enable mask mask mask mask buzzer frequency selection 2khz 4khz 6khz pfd mask mask mask mask ttu621c/ ttr621c su621c-h1 pc0/bz pc1/bzb pa3 pa2 pb3/an3 pb2/an2 pb1/an1 pb0/an0 vss p a1/tmck pa0/int0 pd0 pc3/pwma2 osco osci vdd retb pc2/pwma1
preliminary TTR622c/ ttr621c 2010/06/11 page 30--34 ver. 4.0 . rc oscillator resistor vs. frequency table ? ? (v) l (hz) 51k 5 7.3m 56k 5 6.6m 62k 5 6.1m 68k 5 5.4m 75k 5 4.7m 82k 5 4.4m 91k 5 4.1m 100k 5 3.7m 120k 5 3.1m 150k 5 2.4m 160k 5 2.3m 180k 5 2.0m 200k 5 1.8m 220k 5 1.7m 240k 5 1.6m 300k 5 1.2m 510k 5 714k 1m 5 368k . order information (ttu621 c /ttr621 c ) a. package form : ttu621 c b. chip form : tcu621 c c. wafer base : tdu621 c (ttu622/TTR622) a. package form : ttu622 c b. chip form : tcu622 c c. wafer base : tdu622 c
preliminary TTR622c/ ttr621c 2010/06/11 page 31--34 ver. 4.0 . package information (18-dip) (18-sop)
preliminary TTR622c/ ttr621c 2010/06/11 page 32--34 ver. 4.0 (24-skinny dip) (24-sop)
preliminary TTR622c/ ttr621c 2010/06/11 page 33--34 ver. 4.0 (28-skinny dip) (28-sop)
preliminary TTR622c/ ttr621c 2010/06/11 page 34--34 ver. 4.0 . revise history 2005/9/26 p.15 & p.27 rtc ost 0.5 sec ~2 sec 2006/5/29 p10,p11,p12,p16,p17 p10,p11 : map of memory and i/os add pwmck p12,p16,p17: update pa0&ctl register initial state p16 : update lvrc register func tion description and graph 2006/06/02 p.25, p.27 pwmaen ? pwmben wdt/4 ? wdt/8 2006/07/05 p.3, p.7 update operating voltage update pull high resistance 2006/10/05 p.29 update rc oscillator resi stor vs. frequency table 2006/11/30 p.8 update a.c. characteristics. wa tch dog clock from 8k to 32khz. 2007/5/28 p.20, p.21 : update pc pf graph and description p.7 : iopr1, iopr2, iopr3, iol1, ioh1 @3v ? 5v 2007/0702 p.7 : update d.c. characteristics. p.29 : update rc oscillator resistor vs. frequency table 2007/10/01 p.4 : add 20pin dip/sop package 2010/06/11 p.8: update absolutely max. ratings , operating temperature +70 + 95

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